The prior art uses a method for determining the minimum number of storage registers required to store the minimum number of output states of a circuit. By considering each state of a circuit during each cycle of a clock, a so-called "state diagram" can be constructed which shows the minimum number of states required to provide a desired output. Then, using the equation m = log.sub.2 n wherein m is the number of storage elements and n is the sum of all possible ones of the states, the minimum number of storage elements or memory registers can be determined. The prior art approach is described in detail in the books SWITCHING AND FINITE AUTOMATA THEORY by Z. Kohavi, McGraw-Hill, N. Y., 2nd edition and INTRODUCTION TO VLSI SYSTEMS by C. Mead and L. Conway, Addison-Wesley, Reading, MA, 1980.
In these references, the method of developing a circuit beginning with a waveform pattern is shown in detail. FIGS. 1 and 2 will be used hereinafter to show the prior art method of determining the minimum number of storage registers required to store the states of a clock circuit. Once the number of states is obtained by considering the state of the outputs during each clock cycle, the number of storage registers to store the states is easily determined. To the extent a master-slave storage arrangement is invoked to prevent the circuit from oscillating, the number of storage registers is doubled. Once the number of registers is determined, logical equations can be developed which determine the requirements of the combinatorial logic so the latter, based on its applied input signals, provides the proper input to the storage registers. FIG. 3 shows a clock circuit and its associated combinatorial logic which is developed in part from the "state diagram" of FIG. 2.
To the extent that output conditions during each clock cycle are considered, the prior art method provides the minimum number of states for that regime. However, by simply invoking another regime, that of combining the states occurring during at least a pair of adjacent clock intervals to produce a combined state occurring during a combined clock interval and repeating the combining step until all possible ones of the combined states have been obtained, the number of states can be reduced with a consequent reduction in the number of storage registers and associated combinatorial logic. In this new regime, when a master-slave arrangement is used to prevent circuit oscillation, the reduction obtained is doubled both with respect to the number of storage registers and combinatorial logic circuits.
It is, therefore, an object of the present invention to provide a method for determining the minimum number of states of a circuit using adjacent states of a clock, for example, such that the number of states is reduced and the number of memory units required to store such states is also reduced.
Another object is to provide a method for determining the minimum number of states of a circuit whereby the combinatorial logic requirements of the circuit are reduced.
Still another object is to provide a method for determining the minimum number of states of a circuit whereby the clock rate of a circuit or the storage unit complexity can be reduced.
Yet another object is to provide a clock circuit wherein the desired clock outputs are available using a smaller number of storage registers and less associated combinatorial logic circuitry.
Another object is to provide a clock circuit wherein spuriously occurring spikes and the resulting incorrect circuit operation are eliminated.